1. Field of the Invention
The present invention relates to a molded semiconductor package, and more particularly to a lead frame configuration of a molded semiconductor package.
2. Background Art
Generally, an increase in the operational frequency of a semiconductor device leads to an increase in the inductive components of wires connected between an LSI and a lead frame. On the other hand, an increase in the pin count of a package leads to an increase in the package size, and an increase in the package size results in an increase in the length of the wires connected between the LSI and the lead frame. The increase in the length of the lead frame increases the inductive components of the wires, resulting in degraded high frequency characteristics. In order to reduce the loss components of the wires, conventional molded semiconductor packages are constructed such that: the chip is disposed near the lead frame so as to reduce the length of selected wires; or an intermediate wiring substrate is provided to reduce the length of wires. With these conventional techniques, however, wires other than the selected wires still have a large length. Furthermore, incorporating an intermediate wiring substrate, etc. requires the package to be reconfigured. As a result, it is difficult to manufacture a package having a simple configuration at low cost.
On the other hand, one known method for reducing the inductive components of the wires without reducing their length is to use two wires for each connection to halve the effective inductance. However, this technique requires additional pads to be provided on the LSI and the inner lead frames, since, as described above, it uses two wires for each connection, resulting in an increase in the size of the LSI and the package.
In the case of high frequency LSI, the inductive components of the wires are a factor in waveform degradation. (That is, the inductive components of the wires cause the frequency band of the circuit to be degraded, which leads to Tr/Tf degradation and hence increased jitter, resulting in degradation in the waveform.) Therefore, the length of the wires for high frequency terminals must be reduced as much as possible. Some conventional methods reduce the inductive components of the wires by minimizing their length. See, for example, Japanese Patent Laid-open No. Hei 7-240494 (hereinafter referred to as Patent document 1), No. Hei 8-70090 (hereinafter referred to as Patent document 2) and No. Hei 6-29341 (hereinafter referred to as Patent document 3).
As the number of functions of semiconductor packages has increased, so has the number of pads in these packages, resulting in increased chip size. This is in contradiction to the need to reduce the size of the package so as to be able to mount it in a small space. Overcoming this problem requires a lead frame or inner lead frames that allow even a large chip to be wired in a small package. (That is, the wires must be densely arranged.) Such a lead frame is disclosed in Japanese Patent Laid-open No. 2003-297996 (hereinafter referred to as Patent document 4).
Each high frequency analog chip employs two types of terminals: those requiring that the length of the wires connected to them be reduced to reduce their inductive components; and those requiring that the length of the wires connected to them be increased in order to utilize their inductive components. To achieve such an arrangement, the lead frame must be adapted to allow the length of the wire for each terminal to be appropriately adjusted. To adjust the wire length, one of such lead frames includes a metal portion which is used to increase the area within which the wires from the semiconductor chip are bonded. See, for example, Patent document 1.
Further, there has been a need for a common package having the same configuration (footprint) as conventional packages and capable of accommodating any chip, in order to facilitate packaging and reduce package cost. See, for example, Japanese Patent Laid-open No. 2000-196004 (hereinafter referred to as Patent document 5).
Further, there is also a need for a molded package in which wires having high frequency loss components have been eliminated to meet higher frequency requirements. See, for example, Patent document 1.
Specifically, the technique disclosed in the above Patent document 1 directly bonds a lead to the die pad to reduce the wire length. This technique is disadvantageous in that it can be applied only to this particular lead (for a ground signal). As for the technique disclosed in the above Patent document 2, it reduces the length of the wires for particular pads (or nodes) by using a peripheral wiring region lead frame. This technique can be applied to pads (or pins) disposed at the four corners but cannot be effectively applied to signal lead frames which require that the length of the wires connected to them be reduced to reduce the inductive components. The pads, or nodes, at the four corners are usually used for DC signals such as ground signals and power supply signals. Further problem with this technique is that the length of the wires extending from the lead frame must be increased to accommodate the peripheral wiring region lead frame. The technique described in the above Patent document 3 employs a configuration including two different types of lead frames; a first set of fingers, a second set of fingers. The second set of fingers is provided with a bridge 24. In the above technique, the length of wires is reduced as short as being able to solve the problem of “wire sweep” or “wire wash”. However, the bridge 24 is a necessary component of the configuration in the technique of the Patent document 3.
Further, although the technique described in the above Patent document 4 allows wires to be densely arranged, these wires must have a large length.
Further, according to the above Patent document 1, in order to adjust the wire length, a metal portion is provided to increase the area within which wires from the semiconductor chip are bonded. However, since the metal portion is added to the lead frame and the lead, this technique is disadvantageous in that it can be applied only a single node (for a ground signal).
Further, the technique disclosed in the above Patent document 5 provides a lead frame in which each lead has a few internal connection terminal lands so as to be able to accommodate chips having different sizes. That is, a plurality of peripheral node pad in the lead frame can accommodate each of the different size of chips at the same position. Thus, this technique helps provide a common package but has a problem in that a complicated pattern similar to a conductive lead pattern must be formed on the back surface, since each lead has a plurality of terminal lands.
Further, as described above, there is a need for a molded package in which wires having high frequency loss components have been eliminated to meet higher frequency requirements. However, the technique of Patent document 1 is disadvantageous in that the total length of wires is reduced.